1. Field of the Invention
This invention relates to a frequency determining technique, more particularly to a signal receiving device and a frequency determining circuit that are adapted for receiving an SPDIF (Sony/Philips Digital Interconnect Format) signal and determining a frequency thereof.
2. Description of the Related Art
An SPDIF signal is a digital transmission signal supporting two base frequency types : a 48K base frequency, such as 48 KHz, 96 KHz, and 192 KHz; and a 44.1K base frequency, such as 44.1 KHz, 88.2 KHz, and 176.4 KHz. Since the two base frequency types are close to each other, frequency determination during a receiving process is critical.
A conventional method for frequency determination adopts a two-part technique in which a counter is first used to count bits that are received within a predetermined time period, wherein a frame defined by the SPDIF signal includes two sub-frames, and each of the sub-frames has thirty-two bits. A bit count is then compared to a reference value associated with a 46K base frequency. If the bit count is greater than the reference value, then a type indicator indicating the 48K base frequency is outputted for use in subsequent audio signal processing. Otherwise, the type indicator indicating the 44.1K base frequency is outputted.
However, on account of interference on a signal transmission channel, such as that resulting from electromagnetic effects, and/or a state in which clock frequencies used by a transmitting end and a receiving end are inconsistent, signals received by the receiving end often fluctuate around the 46K base frequency. Accordingly, when a base frequency that is determined by the conventional method changes, the type indicator that is outputted enters an unlocked state with respect to the base frequency, and re-enters a locked state with respect to another base frequency. Undesirably, data received during a process of changing frequency locking state is neglected. Moreover, if fluctuation persists, the type indicator can remain in the unlocked state for a prolonged period and fail to attain the lock state.